The present invention is generally related to operational amplifiers. More particularly, the present invention relates to an improved folded-cascode amplifier that is suitable for high-speed operation.
A conventional operational amplifier (300) is illustrated in FIG. 3. The operational amplifier (300) includes six transistors (M31-M36), and three current sources (I31-I33).
Transistor M31 includes a source that is connected to node N31, a gate that is connected to V31, and a drain that is connected to node N32. Transistor M32 includes a source that is connected to node N31, a gate that is connected to V32, and a drain that is connected to node N33. Transistor M33 includes a source that is connected to node N33, a gate that is connected to VCASN. Transistor M34 includes a source that is connected to node N32, a gate that is connected to VCASN, and a drain that is connected to node N34. Transistor M35 includes a source that is connected to VDD, a gate that is connected to node N34, and a drain that is connected to OUT. Transistor M36 includes a source that is connected to VDD, and a gate and drain that are connected to node N34. Current source I31 is connected between VDD and node N31. Current source I32 is connected between node N32 and VSS. Current source I33 is connected between N33 and VSS.
In operation, transistors M35 and M36 are arranged as a current mirror, while transistors M33 and M34 are cascode transistors that are biased by VCASN. A differential voltage is applied across V31 and V32. Transistors M31 and M31 cooperate with current source I31 to operate as a differential pair circuit that steers current to nodes N32 and N33 in response to the differential voltage. The current that is provided to nodes N32 and N33 corresponds to I/2 when V31 and V32 are equal.
According to an example of the present invention, an amplifier circuit is provided that include a differential pair circuit, a current mirror circuit, and a cascode circuit. The differential pair circuit is arranged to steer a tail current between first and second nodes in response to a differential signal. The current mirror circuit is coupled to the first and second nodes, wherein the current mirror circuit is arranged to provide a reflected current to the second node when activated by at least a portion of the tail current. The cascode circuit is biased by a cascode current, wherein the cascode circuit is coupled between a cascode output node and the first node such that first node is isolated from the cascode output node by the cascode circuit, wherein the amplifier is arranged to provide an output current to the cascode output node.
According to another example of the present invention, an apparatus is provided that includes a differential pair circuit, a current mirror circuit, and a cascode circuit. The differential pair circuit includes a first current source that is coupled to a third node, a first transistor that is coupled between a first node and the third node, and a second transistor that is coupled between a second node and the third node. The first and second transistors are arranged to steer a tail current from the first current source to the first and second nodes in response to a differential signal. The current mirror circuit is coupled to the first and second nodes. The current mirror circuit includes a fourth transistor that is coupled between the first node and a fourth node, a fifth transistor that is coupled to the first node and the second node, and a sixth transistor that is to the first node and the fourth node. The fifth and sixth transistors are commonly controlled by a signal from the first node such that a reflected current is provided to the second node when the sixth transistor is activated by at least a portion of the tail current. The cascode circuit includes a second current source that is coupled to a fifth node, and a third transistor that is coupled between the fifth node and the second node. The third transistor is biased by a cascode bias signal such that the amplifier is arranged to provide a cascode output current to the fifth node.
According to one aspect, the first current source is arranged to provide a tail current having a magnitude corresponding to I1, while the second current source is arranged to provide a cascode current having a magnitude corresponding to I2. The fifth and sixth transistors have associated sizes that are related to one another by a ratio that corresponds to: 1+2*(I2/I1).
According to another aspect, the second transistor is arranged to provide the tail current to the second node when the fifth transistor is deactivated, and the fifth transistor is arranged to conduct another current having a magnitude corresponding to I1+2*I2 when the second transistor is deactivated.
According to still another aspect, the first current source is arranged to provide a tail current having a magnitude corresponding to I1, the second current source is arranged to provide a cascode current having a magnitude corresponding to I2, and the third and fourth transistors have associated sizes that are related to one another by a ratio that corresponds to: 2*(I2/I1).
According to a further aspect an output stage is provided that includes an eighth transistor that is coupled to the fifth node and an output node. The eighth transistor is arranged to provide an output signal to the output node in response to signals at the fifth node. A capacitor (C) may be coupled between the second node and the output node, wherein the first current source is arranged to provide a tail current having a magnitude corresponding to I1, and the second current source is arranged to provide a cascode current having a magnitude corresponding to I2 such that the amplifier charges capacitor C with a positive slew rate (SRP) corresponding to: SRP=(I1+I2)/C. Furthermore, the fifth transistor may be ratioed in size to the sixth transistor according to a factor (X). When transistor M1 has a parasitic capacitance (CP) that is coupled to node N3, the amplifier discharges capacitor C with a negative slew rate (SRN) corresponding to: SRN=((X*I1)xe2x88x92I2)/(C+CP). When the value associated with the parasitic capacitance (CP) is much less than the value associated with the capacitor (C), the negative slew rate (SRN) is SRN=((X*I1 )xe2x88x92I2)/C.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, the following detail description of presently preferred embodiments of the invention, and the appended claims.